Let me preface my post here with the note that I am getting all my information from the AMD64 Arcitecture Programmer's Manual: Volume 1.
Section 1.1.1 shows a diagram of the registers that shows the old ia32 registers, and the new AMD64 registers. You will note, that the first 8 GPRs are labeled EAX, EBX, etc. Then AMD adds the R8-R16 Registers, and also extends the old registers (EAX, EBX, etc.) to 64 bit. The EIP register is expanded to the RIP register for 64 bit code, and the registers XMM8-XMM16 are added.
I must now correct two of your comments:
(1) That the opcodes cannot be changed. That is not true. I remember doing some reading many years back, about how to use debug (yes that terrible dos program) to generate code that would use the extended registers. I don't know exactly what the opcodes where, but there was an opcode prefix that would be used before the register to tell the processor that the next register refferenced would be an extended register.
So, if let's say the hex code for ADD AX, BX looked like this:
3F 5E 2C (Yes, I just randomly put out some numbers)
Then the ADD EAX, EBX would look like this:
3F FF 5E FF 2C (assuming that FF was the hex code for the EAX extention)
(2) The seccond point that I must correct, is that Intel makes the standards. This is not true. I guess you haven't heard of Intel's new ultra-highend P4 EM64T that uses the SAME AMD64 opcodes to do 64bit programming. (I bet Microsoft made them do it.) In this case, AMD had the standard first, and still has the standard, because the EM64T (or whatever Intel calls it), is slower, and more expensive then the AMD counterpart (http://www.anandtech.com/linux/showdoc.aspx?i=2158
). Let me ammend that, the EM64T does almost as good as an Athlon64! If you wanted a real comparison an Opteron would be better.
Anyway, that's my issues with the last post